Although more and more functions are incorporated into a chip, the pin number of a chip tends to be reduced in order to minimize the chip size. Practically, power and ground pins of the chip are the targets to be reduced. Alternatively, the chip size can also be reduced by decreasing the pad width of the power and ground pins or the clearance between pins of the chip.
In above cases, however, the phenomenon of power bounce or ground bounce is likely to occur. Since the number or the pad width of the power pins is reduced, the power supply is limited. When a lot of output signals of the output devices in the chip are simultaneously switched to high electric levels, there would be no sufficient power supply for the level switching operations. Therefore, a jumping and unstable phenomenon in the output signal occurs, which is so-called as “power bounce”. Therefore, the electric level of the output signal from the output device will continuously toggle, resulting in possible errors of another chip electrically connected to the output end of the present chip.
Likewise, when the number or the pad width of the ground pins is not great enough or the distance between pins is too small, “ground bouce” may also occur. It is because the toggling action of an output signal will affect the electric level of an adjacent output signal via the ground pin so as to result in a continuous toggle phenomenon. The continuous toggle phenomenon is even significant when a plurality of adjacent output devices are simultaneously switched to the ground state. Under this circumstance, the ground pin itself will be jumping and unstable so as to result in ground bounce. The power/ground bounce, if occurs, adversely affects the output stability of the chip.
Please refer to FIG. 1 which is a diagram showing the waveform associated with exemplified output devices of a chip. The signal bounces of the output signals from the output devices and the ground signal at the grounding line are shown. As shown in the upper part of FIG. 1, a chip C includes output devices CQ1 and CQ2 with CMOS structures. The output device CQ1 includes transistors Q11 and Q12, and is electrically connected to an output pad (pad1) by an output end thereof. The output device CQ2 includes transistors Q21 and Q22, and is electrically connected to an output pad (pad2). Further, a grounding line VSSO provides the grounding path of the output devices CQ1 and CQ2.
When a high electric level signal is inputted to the input end C12 of the output device CQ2, an output signal outputted from the output pad “pad2” of the output device CQ2 is a stably low electric level signal, which is at a ground state. Once a high electric level signal is also inputted to the input end CI1 of the adjacent output device CQ1, signal bounce may appear at the output pad “pad1” before the electric level becomes stably low, i.e. at a ground state, as shown in curve A of FIG. 1. The situation is likely to occur when the pin number or pad width of the chip C is insufficient or the clearance between the output devices CQ1 and CQ2 is too small. Due to the signal bounce, the electric level of the output signal at the output pad “pad2” is influenced by the coupling effect of the grounding line VSSO. The electric level of the output signal is thus bouncing. Moreover, the electric level of the ground signal at the ground line VSSO is also disturbed.
For solving the above power-bounce or ground-bounce problems, lots of attempts have been made, which include enhancing the driving capability of the chip by increasing the number or pad width of power pins, introducing interleaving driving operations by adding delay gate(s) so as to avoid simultaneously active high or active low status, increasing the slew rate of the electric level toggle, or enlarging the clearance between the output devices. Unfortunately, the chip size is inevitably increased or the chip design is hardly feasible due to high operation frequency accordingly.
A terminator structure conventionally used for solving the signal reflection problem resulting from rapid signal transmission may have a little effect on solving the signal bounce problem. Please refer to FIG. 2 which is a schematic diagram illustrating the terminator structure. In this structure, pins, e.g. pins P1, P5 and Pn among the output pins P1˜Pn of the chip C, are connected to a resistor R1 and a diode D1, a resistor R5 and a diode D5, and a resistor Rn and a diode Dn, respectively. The resistors R1, R5 and Rn are connected to a power source +Vcc. This structure, although solving some signal bounce problem, cannot solve the power/ground bounce problem. It is because this terminator structure can work well to inhibit signal bounce only under stable power/ground signals.
Therefore, the purpose of the present invention is to develop a signal bounce inhibiting device to deal with the above situations encountered in the prior art.